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SPICLK (Output)
Input Signals:
SPIMISO
t NIIVKH
t NIIXKH
(See Note)
Output Signals:
t NIKHOX
t NIKHOV
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 36. SPI AC Timing in Master Mode (Internal Clock)
2.6.13
Asynchronous Signal Timing
Table 49. Signal Timing
Input
Output
Characteristics
Symbol
t IN
t OUT
Type
Asynchronous
Asynchronous
Min
One CLKIN cycle 1
Application dependent
Note:
1. Relevant for EE0, IRQ[15–0], and NMI only.
The following interfaces use the specified asynchronous signals:
?
Note:
?
?
?
?
?
GPIO . Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are
not selected.
When used as a GPI, the input should be driven until it is acknowledged by the device; the GPIO input status is read
from a register.
EE port. Signals EE0, EE1, EE2_0, EE2_1, EE2_2, and EE2_3.
Boot function . Signal STOP_BS.
I 2 C interface . Signals I2C_SCL and I2C_SDA.
Interrupt inputs . Signals IRQ[15–0] and NMI.
Interrupt outputs . Signals INT_OUT and NMI_OUT (pulse width is 10 ns).
Figure 37 shows the behavior of the asynchronous signals.
t IN
Input
t OUT
Output
Figure 37. Asynchronous Signal Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
62
Freescale Semiconductor
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